1. Field
The present disclosure generally relates to a chip package for semiconductor dies or chips. More specifically, the present disclosure relates to a chip package that includes mechanically reinforced positive features that facilitate alignment of semiconductor chips in a multi-chip module (MCM) that includes the chip package.
2. Related Art
As integrated-circuit (IC) technology continues to scale to smaller critical dimensions, it is increasingly difficult for existing interconnects to provide suitable communication characteristics, such as: high bandwidth, low power, reliability and low cost. Engineers and researchers are investigating chip stacking in multi-chip modules (MCMs) to address these problems, and to enable future high-density, high-performance systems.
However, it is difficult to bond chips to each other and to carriers (such as printed circuit boards) in chip stacks using existing assembly techniques because of stringent requirements for alignment accuracy and manufacturing throughput. For example, if chips are bonded to each other using a silicone-based adhesive, a pick-and-place tool and non-standard fixturing may be needed to obtain the desired alignment.
Alternatively or additionally, chips in an MCM may be assembled using positive and/or negative features, for example, using balls and pits, in which adjacent chips in the MCM are aligned by placing the balls into collocated pits on surfaces of the chips. This existing assembly technique can provide high alignment accuracy among the chips in the MCM. However, it typically involves multiple assembly operations, which makes assembly of the chip package complicated, time-consuming and expensive.
In addition, fabricating the positive and/or negative features can be challenging. For example, relative to features that are fabricated using an additive process (in which material is added), features that are fabricated using a subtractive process (in which material is removed) tend to be more structurally stable and, in general, are also able to withstand sufficient shear force to allow the features to make and to maintain alignment. However, many subtractive fabrication processes are incompatible with other semiconductor fabrication processes or may interfere with the function of a semiconductor wafer.
As a consequence, additive processes often are preferred when fabricating positive and negative features. However, because of poor adhesion to the substrates in the chips, the resulting ‘additive’ features often fail when subjected to lateral shear forces, such as those associated with different coefficients of thermal expansion and lateral misalignment of the chips in the MCM. Consequently, additive features are often unreliable, which can prevent them from properly aligning the chips in the MCM.
Hence, what is needed is a chip package without the above-described problems.